Package structure and manufacturing method thereof

ABSTRACT

A package structure and a manufacturing method thereof are provided. The package structure includes a circuit carrier, a substrate, a die, a plurality of conductive wires and an encapsulant. The substrate is disposed on the circuit carrier and includes a plurality of openings. The die is disposed between the circuit carrier and the substrate. The conductive wires go through the openings of the substrate to electrically connect between the substrate and the circuit carrier. The encapsulant is disposed on the circuit carrier and encapsulates the die, the substrate and the conductive wires.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of U.S. provisionalapplication Ser. No. 62/410,851, filed on Oct. 21, 2016. The entirety ofthe above-mentioned patent application is hereby incorporated byreference herein and made a part of the specification.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention generally relates to a package structure and amanufacturing method thereof and more particularly relates to asemiconductor package structure.

2. Description of Related Art

In order for electronic product design to achieve being light, slim,short, and small, semiconductor packaging technology has keptprogressing, in attempt to develop products that are smaller in volume,lighter in weight, higher in integration, and more competitive in themarket. For example, 3D stacking technologies such as package have beendeveloped to meet the requirements of higher packaging densities. Assuch, how to increase the number of I/O connections with lowermanufacturing cost has become a challenge to researchers in the field.

SUMMARY OF THE INVENTION

The disclosure provides a package structure and manufacturing methodthereof, which reduces manufacturing cost and increases the number ofI/O connections.

The disclosure provides a manufacturing method of a package structure.The method includes at least the following steps. A die is disposed on acircuit carrier. A substrate is disposed on the die. The substrateincludes a plurality of openings. A plurality of conductive wires goingthrough the openings of the substrate are formed to form electricalconnection between the substrate and the circuit carrier. An encapsulantis formed on the circuit carrier to encapsulate the die, the substrateand the conductive wires.

The disclosure provides a package structure including a circuit carrier,a substrate, a die, a plurality of conductive wires and an encapsulant.The substrate is disposed on the circuit carrier and includes aplurality of openings. The die is disposed between the circuit carrierand the substrate. The conductive wires go through the openings of thesubstrate to electrically connect between the substrate and the circuitcarrier. The encapsulant is disposed on the circuit carrier andencapsulates the die, the substrate and the conductive wires.

Based on the above, the substrate disposed on the die is conducive toform the conductive wires. In addition, the substrate may serve as theconductive interface for further electrical connection. Moreover, sincethe vias are formed on the encapsulant to expose at least a portion ofthe substrate, it makes the package structure more flexible forcompatibility with different device applications.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the disclosure, and are incorporated in and constitutea part of this specification. The drawings illustrate embodiments of thedisclosure and, together with the description, serve to explain theprinciples of the disclosure.

FIG. 1A to FIG. 1D are schematic cross-sectional views illustratingmanufacturing method of a package structure according to an embodimentof the disclosure.

FIG. 2 is a schematic top view illustrating a substrate of a packagestructure according to an embodiment of the disclosure.

FIG. 3 is a schematic cross-sectional view illustrating a packagestructure according to an embodiment of the disclosure.

FIG. 4 is a schematic cross-sectional view illustrating a packagestructure according to an embodiment of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the disclosure, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

FIG. 1A to FIG. 1D are schematic cross-sectional views illustratingmanufacturing method of a package structure according to an embodimentof the disclosure. FIG. 2 is a schematic top view illustrating asubstrate of a package structure according to an embodiment of thedisclosure. Referring to FIG. 1A, a circuit carrier 110 is provided. Thecircuit carrier 110 may have a top surface S1 and a bottom surface S2opposite to the top surface S1. For example, the circuit carrier 110 mayinclude a core layer 112, a top circuit layer 114 disposed on the topsurface S1 and the bottom circuit layer 116 disposed on the bottomsurface S2 of the circuit carrier 110. In other word, the core layer 112is disposed between and electrically connects the top circuit layer 114and the bottom circuit layer 116. In some embodiments, the top circuitlayer 114 may include a plurality of conductive pads 114 a and thebottom circuit layer 116 may include a plurality of conductive pads 116a used for electrical connection. Moreover, the conductive pads 114 a ofthe top circuit layer 114 and the conductive pads 116 a of the bottomcircuit layer 116 may be formed by the same material copper, solder,gold, nickel, or the like and the same process such as photolithographyand etching processes. In other embodiments, the conductive pads 114 aof the top circuit layer 114 and the conductive pads 116 a of the bottomcircuit layer 116 may be formed by different materials and/or differentprocesses according to the design requirement.

The core layer 112 may include embedded circuit layers serving as anintermediate circuit layer to electrically connect the top circuit layer114 and the bottom circuit layer 116. For example, the core layer 112may include a base layer and a plurality of conductive vias penetratingthrough the base layer. In addition, the two opposite ends of theconductive vias of the core layer 112 may electrically connect to theconductive pads 114 a of the top circuit layer 114 and the conductivepads 116 a of the bottom circuit layer 116. In some embodiments, thecircuit carrier 110 may include a plurality of conductive structures 118formed on the bottom surface S2. For example, a material of theconductive structures 118 may include copper, tin, gold, nickel or othersuitable conductive material, which is not limited thereto. Moreover,the conductive structures 118 may, for example, be conductive bumps,conductive pillars or solder balls formed by a ball placement processand a reflow process. It should be noted that other possible forms andshapes of the conductive structures 118 may be utilized for furtherelectrical connection. In some embodiments, the conductive structures118 may form a fine pitched array arranged on the bottom surface S2 ofthe circuit carrier 110 as required in the subsequent processes.

In addition, a die 120 is bonded on the top surface S1 of the circuitcarrier 110. The die 120 may be electrically connected to the circuitcarrier 110 through flip-chip bonding. In some embodiment, an activesurface (not illustrated) of the die 120 may be coupled to theconductive pads 114 a of the top circuit layer 114 of the circuitcarrier 110 through a plurality of conductive bumps 122 facing towardthe circuit carrier 110. The conductive bumps 122 may be copper bumps.In some embodiments, solders (not illustrated) may be applied ontosurfaces of the conductive bumps 122 to couple with the conductive pads114 a of the top circuit layer 114 of the circuit carrier 110.Furthermore, the die 120 may be, for example, an ASIC(Application-Specific Integrated Circuit). In some embodiments, the die120 may be used to perform logic applications. However, it construes nolimitation in the disclosure. Other suitable active devices may also beutilized as the die 120. Furthermore, an underfill (not illustrated) maybe formed on the top surface S1 of the circuit carrier 110 and also inthe gap between the active surface of the die 120 and the top surface S1of the circuit carrier 110 to enhance the reliability of the die bondingprocess.

Referring to FIG. 1B and FIG. 2, a substrate 130 is disposed on the die120. The substrate 130 may include a plurality of openings 130 a. Amaterial of the substrate 130 may include conductive materials (e.g.,aluminium, copper, nickel, gold or alloys thereof, etc.), non-conductivematerials (e.g., glass, rigid plastic or the like, etc.) or combinationthereof. It should be noted that other suitable material may be adaptedas the substrate 130 as long as the material is able to withstand theprocesses performed thereon. In addition, the size, the shape and thethickness of the substrate 130 construe no limitation in the disclosure.In addition, the openings 130 a of the substrate 130 may be formedthrough mechanical drilling, photolithography and etching or othersuitable methods, which is not limited thereto. Moreover, referring toFIG. 2, the openings 130 a of the substrate 130 may be formed on thesubstrate 130 surrounding the periphery of the die 120. Moreover, theopenings 130 a may be staggered from the die 120. It should be notedthat the number of the openings 130 a construes no limitation in thedisclosure.

In some embodiments, a conductive layer 130 b may be formed on a surface130 c opposite to the die 120 of the substrate 130 by means of physicalvapor deposition (PVD), chemical vapor deposition (CVD), electro-platingor other suitable metal deposition process, which is not limitedthereto. A material of the conductive layer 130 b may include aluminum,copper, gold, silver or other suitable electrically conductive material.However, it construes no limitation in the disclosure. In otherembodiments, the conductive layer 130 b may be patterned to form as aplurality of conductive connectors such as contact pads (e.g., aluminiumpads, copper pads or the like). In other word, the substrate 130 notonly serves as the conductive connectors for performing subsequentelectrical bonding process but also provides a spacer function toprevent damage to the die 120.

The substrate 130 may be bonded to the die 120 through an adhesive layer140. In some embodiments, the adhesive layer 140 may be a die attachfilm or formed from the adhesive material including an epoxy resin. Theadhesive layer 140 may be formed by methods such as spin coating, injectprinting or other suitable methods for providing a structural support toeliminate the need for mechanical clamping between the die 120 and thesubstrate 130.

Referring to FIG. 1C, the substrate 130 and the circuit carrier 110 areelectrically connected by a plurality of conductive wires 150 that gothrough the openings 130 a of the substrate 130. For example, theconductive wires 150 may be formed through a wire bonder (notillustrated). The types of the wire bonder may include wedge bond, ballbond, or other suitable wire bonder according to the design requirement.Moreover, the conductive wires 150 are connected between the conductivelayer 130 b of the substrate 130 and the circuit carrier 110. A materialof the conductive wires 150 may be gold, copper, or other suitablematerial. However, it construes no limitation in the disclosure. In someembodiments, the conductive wires 150 may be formed from the substrate130 to the circuit carrier 110. In other embodiments, the conductivewires 150 may be formed from the circuit carrier 110 to the substrate130. The forming sequence of the conductive wires 150 may depend on thedesign requirement. In some embodiments, since the conductive wires 150are formed between the conductive layer 130 b of the substrate 130 andthe circuit carrier 110 and through the openings 130 a of the substrate130, the size of the openings 130 a of the substrate 130 may be largeenough for the wire bonder to pass through.

Moreover, a peak (not illustrated) of each of the conductive wires 150is defined as the highest point relative to the two ends of each of theconductive wires 150 after connecting the substrate 130 and the circuitcarrier 110. In addition, a loop height H of each of the conductivewires 150 is defined as a distance between the peak of each of theconductive wires 150 and the circuit carrier 110. It should be notedthat the value of the loop height H of each of the conductive wires 150depends on the types of the wire bonder and/or the design requirement.

In addition, each of the conductive wires 150 may include a firstsegment 150 a, a central segment 150 b and a second segment 150 c. Thefirst segment 150 a may be coupled to the circuit carrier 110, thesecond segment 150 c may be coupled to the substrate 130, and thecentral segment 150 b may be the segment between the first segment 150 aand the second segment 150 c. In some embodiments, the first segment 150a may be formed below the substrate 130 and the second segment 150 c maybe formed above the substrate 130. The second segment 150 c of each ofthe conductive wires 150 may be formed with an arc shape. In addition,the peak of each of the conductive wires 150 may be the highest point ofthe second segment 150 c. Furthermore, the central segment 150 b maypass through a corresponding opening 130 a of the substrate 130. In someembodiments, the loop height H of each of the conductive wires 150 maybe greater than a distance D1 between the surface 130 c of the substrate130 and the top surface S1 of the circuit carrier 110.

Referring to FIG. 1D, an encapsulant 160 is formed on the circuitcarrier 110 to encapsulate the die 120, the substrate 130, the adhesivelayer 140 and the conductive wires 150. In some embodiments, a thicknessof the encapsulant 160 is greater than the loop height H of theconductive wires 150. In addition, the encapsulant 160 may include amolding compound formed by a molding process. In some embodiments, theencapsulant 160 may be formed by an insulating material such as epoxy,resins, moldable polymer, or other suitable resins. However, itconstrues no limitation in the disclosure.

Thus, the package structure 10 have the substrate 130 stacked on the die120 to serve as the conductive interface for performing the wire bondingprocess and form an additional interposer within the package structure10 unnecessary for further electrical connection. In this way, asimplified manufacturing method with lower manufacturing cost may beachieved.

FIG. 3 is a schematic cross-sectional view illustrating a packagestructure according to an embodiment of the disclosure. Referring toFIG. 3, the manufacturing methods of a package structure 20 is similarto the manufacturing methods of the embodiment illustrated in FIG. 1A toFIG. 1D. The detailed descriptions are omitted herein. The differencebetween the present embodiment and the embodiment illustrated in FIG. 1Ato FIG. 1D lies in that a plurality of vias 160 a may be formed on theencapsulant 160 extending from a surface 160 b of the encapsulant 160 tothe surface 130 c of the substrate 130 to expose at least a portion ofthe substrate 130 so as to form the package structure 20 after formingthe encapsulant 160 on the circuit carrier 110 as illustrated in FIG.1D.

For example, the encapsulant 160 may be removed by laser ablation, laserdrilling, mechanical drilling, or other suitable methods to form thevias 160 a. It should be noted that the number of the vias construes nolimitation in the disclosure. Moreover, for example, a depth D2 of eachof the vias 160 a may be controlled by the power of the laser, the speedat which the laser is moved, and/or other processing factors. In someembodiments, the depth D2 of each of the vias 160 a may be equal to adistance D3 between the surface 130 c of the substrate 130 and thesurface 160 b of the encapsulant 160 farthest from the circuit carrier110. In some embodiments, a portion of the vias 160 a may be formedwithin the area of the die 120. Since the substrate 130 provides aspacer function, the reliability of the die 120 may not be affected whenforming the portion of the vias 160 a formed within the area of the die120.

In some embodiments, the vias 160 a may be staggered from the openings130 a of the substrate 130. As such, when forming the vias 160 on theencapsulant 160, the conductive wires 150 may not be affected, therebyensuring the electrical connection between the substrate 130 and thecircuit carrier 110. In some embodiments, the vias 160 a may be formedcorresponding to the conductive layer 130 b to form conductive vias. Assuch, the vias 160 a may serve as the conductive path between thepackage structure 20 and the external connectors. Furthermore, thepackage structure 20 may achieve the fine pitch requirement and increasethe number of I/O connections. Therefore, the package structures 20 maybe compatible with high-end device applications and advanced front-endtechnology node, of which a number of I/O connections is higher, and apad pitch of each die is narrower.

FIG. 4 is a schematic cross-sectional view illustrating a packagestructure according to an embodiment of the disclosure. Referring toFIG. 4, the manufacturing methods of a package structure 30 is similarto the manufacturing methods of the embodiment illustrated in FIG. 3.The detailed descriptions are omitted herein. As shown in FIG. 4, thevias 160 a may be filled with a conductive element 170 and asemiconductor element 200 may be stacked on the encapsulant 160 and alsoelectrically connected to the substrate 130 to form the packagestructure 30.

For example, the conductive element 170 filled in the vias 160 a may beformed as conductive bumps, conductive pillars, conductive pads, orother conductive connectors. In some embodiments, the conductive element170 may be formed by having a conductive material (e.g., aluminum,copper, nickel, gold, silver, solder, or alloy, etc.) deposited on thesurface 160 b of the encapsulant 160 and fill the vias 160 a throughevaporation, electro-plating, ball drop, screen printing, or othersuitable methods. In addition, the conductive material may be patternedthrough a photolithography and an etching process to form the conductiveelement 170. However, the material and the forming process of theconductive element 170 construe no limitation in the disclosure. Assuch, after the vias 160 a are filled with the conductive element 170,the package structure may have the conductive elements 170 and theconductive structures 118 of the circuit carrier 110 on the two oppositesides of the semiconductor package 30, thereby increasing the number ofI/O connections.

In some embodiments, the vias 160 a may be filled with solder materialsby paste print process to enable the ball grid array (BGA)interconnections. In other embodiments, the vias 160 a may be used tobuild up the interconnect structure (e.g. the conductive element 170)for further electrically connection to the semiconductor element 200. Inother embodiments, the semiconductor element 200 may include DRAM, NANDflash memory or other suitable active devices, which is not limitedthereto. Moreover, the semiconductor element 200 may further include aplurality of conductive structure 202 correspondingly coupled to theconductive elements 170, for example. In addition, the conductivestructures 202 may be conductive bumps, conductive pillars or solderballs formed by a ball placement process and a reflow process. In otherword, the semiconductor element 200 may be stacked on the encapsulant160 and electrically connected to the circuit carrier 110 through theconductive elements 170, the substrate 130, and the conductive wires 150to form the package structure 30.

In some embodiments, the package structure 30 may sometimes be referredto as a package-on-package (POP) structure. Therefore, the packagestructure may be conducive for further electrical connection, since thesubstrate 130 may serve as the conductive interface and the vias 160 aare formed on the encapsulant 160 to expose at least a portion of thesubstrate 130. As such, it makes the package structure more flexible forcompatibility with different device applications.

Based on the above, the substrate disposed on the die is not onlyconducive to form the conductive wires but also provides a spacerfunction to prevent the damage of the die in the subsequent processes.In addition, when the vias are formed on the encapsulant to expose atleast a portion of the substrate, the conductive wires may serve as theconductive interface for further electrical connection. Therefore, thepackage structure may achieve the fine pitch requirement and alsoincrease the number of I/O connections. As such, it makes the packagestructure more flexible for compatibility with different deviceapplications. As a result, it may open the possibility to variouspackage designs with lower manufacturing cost.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentdisclosure without departing from the scope or spirit of the disclosure.In view of the foregoing, it is intended that the present disclosurecover modifications and variations of this disclosure provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A manufacturing method of a package structure,comprising: disposing a die on a circuit carrier; disposing a substrateon the die, wherein the substrate comprises a plurality of openings;forming a plurality of conductive wires going through the openings ofthe substrate to form electrical connection between the substrate andthe circuit carrier; and forming an encapsulant on the circuit carrierto encapsulate the die, the substrate and the conductive wires.
 2. Themanufacturing method of a package structure according to claim 1,wherein the die is disposed on the circuit carrier through flip-chipbonding.
 3. The manufacturing method of a package structure according toclaim 1, wherein disposing the substrate on the die is adheringdisposing the substrate and the die to each other using an adhesivelayer.
 4. The manufacturing method of a package structure according toclaim 1, wherein forming a plurality of conductive wires is forming aplurality of conductive wires through a wire bonder.
 5. Themanufacturing method of a package structure according to claim 1,wherein each of the conductive wires comprises a first segment connectedto the circuit carrier, a second segment connected to the substrate anda central segment connected between the first segment and the secondsegment, the first segment is formed below the substrate, the secondsegment is formed above the substrate and the central segment is formedin one of the corresponding openings of the substrate.
 6. Themanufacturing method of a package structure according to claim 1,further comprising: forming the openings on the substrate, wherein theopenings surround the periphery of the die.
 7. The manufacturing methodof a package structure according to claim 1 further comprising: forminga plurality of vias on the encapsulant to expose at least a portion ofthe substrate.
 8. The manufacturing method of a package structureaccording to claim 7, wherein a depth of the vias is a distance betweena surface of the substrate farthest from the circuit carrier and asurface of encapsulant farthest from the circuit carrier.
 9. Themanufacturing method of a package structure according to claim 7,further comprising: filling the vias with a conductive element.
 10. Themanufacturing method of a package structure according to claim 9,further comprising: disposing a semiconductor element on the encapsulantand electrically connecting the semiconductor element to the substratethrough the vias.
 11. A package structure, comprising: a circuitcarrier; a substrate, disposed on the circuit carrier, wherein thesubstrate comprises a plurality of openings; a die, disposed between thecircuit carrier and the substrate; a plurality of conductive wires,going through the openings of the substrate to electrically connectbetween the substrate and the circuit carrier; and an encapsulant,disposed on the circuit carrier, wherein the encapsulant encapsulatesthe die, the substrate and the conductive wires.
 12. The packagestructure according to claim 11, further comprising: an adhesive layer,disposed between the circuit carrier and the substrate.
 13. The packagestructure according to claim 11, wherein the die comprises a pluralityof conductive bumps facing toward the circuit carrier, and the die iselectrically connected to the circuit carrier through the conductivebumps.
 14. The package structure according to claim 11, wherein a loopheight of each of the conductive wires is greater than a distancebetween a surface of the substrate opposite to the circuit carrier and asurface of the circuit carrier facing toward the substrate.
 15. Thepackage structure according to claim 11, wherein each of the conductivewires comprises a first segment connected to the circuit carrier, asecond segment connected to the substrate and a central segmentconnected between the first segment and the second segment, the firstsegment is disposed below the substrate, the second segment is disposedabove the substrate and the central segment is disposed in one of thecorresponding openings of the substrate.
 16. The package structureaccording to claim 11, wherein the openings are arranged on thesubstrate surrounding the periphery of the die.
 17. The packagestructure according to claim 11, wherein the encapsulant comprises aplurality of vias exposing at least a portion of the substrate.
 18. Thepackage structure according to claim 17, wherein a depth of the vias isa distance between a surface of the substrate farthest from the circuitcarrier and a surface of the encapsulant farthest from the circuitcarrier.
 19. The package structure according to claim 17, wherein theencapsulant comprises a conductive element disposed in the vias.
 20. Thepackage structure according to claim 19, further comprising: asemiconductor element, disposed on the encapsulant, wherein thesemiconductor element is electrically connected to the substrate throughthe vias.